Scalar single-precision, the A64 counterpart of the x86-64 SSE scalar
lowering (L13c). Every word below was assembled from the same mnemonic by
GNU `as` on this host; the laws in Compiler.MachineAArch64Proof carry the
bytes.
FP data-processing, two sources:
0001 1110 0 01 Rm opcode 10 Rn Rd
with opcode 0 FMUL, 1 FDIV, 2 FADD, 3 FSUB. The Rm field is bits 16-20, so
byte 2 is 32 + Rm; the `10` in bits 10-11 is the 8 in byte 1.
984def aarch64FloatRdByte0 =
985 (lambda unrestricted register : (family AArch64FloatRegister) .
986 (aarch64FloatRegisterCode register))The compiler supplied declaration spans and resolved links from this source snapshot. This page does not assert that this file belongs to a checked closure.