Wire layout is a compiler decision, separate from the host command semantics.
V2 preserves the packed x86 image. V3 aligns every record to four bytes so
inline machine routines can execute on an ISA with aligned instruction fetch.
Both have a 176-byte header and 232-byte fixed record. V3 changes magic and
version to ALPXPHY3 / 3 and adds zero padding AFTER the error identity:
recordExtent = roundUp(232 + payloadExtent + auxiliaryExtent + errorExtent, 4)
The three content extents retain their exact meaning; padding is never a
syscall payload, copied data, telemetry field or diagnostic identity. The
reader checks the rounded extent before dispatch and advances by that extent.
The image base must itself be aligned. Compiler.ELF plus the AArch64 assembler
establish this for the maintained host. V2 readers must reject V3 and vice versa.
17family NativePhysicalImageFormat : Type 0
18constructor NativePhysicalImagePackedV2
19constructor NativePhysicalImageAlignedV3The compiler supplied declaration spans and resolved links from this source snapshot. This page does not assert that this file belongs to a checked closure.