One SHA-256 block-compression algorithm, specialized to a host instruction emitter.
The emitter owns register assignment, instruction selection and branch
flags. Loads/stores are little-endian and permit unaligned access; 8/32-bit
loads zero-extend. Word operations wrap at 64 bits, shifts are logical, and
8/32-bit stores truncate. AddImm sign-extends its 32-bit operand and sets
zero status; CmpImm supplies unsigned, zero and signed-negative status. Label and move
operations preserve that status. These obligations are tested on each host.
Registers are logical roles inherited from the original implementation:
RDI/RSI/RDX/RCX/R8/R9 carry the six arguments; the remaining names denote
scratch values. The emitter chooses physical registers and preserves its
calling convention. The fixed work-area slots are part of this algorithm,
not per-system addresses. Callers supply writable, nonoverlapping bounded
buffers, a positive block count and body length, and valid SHA padding.
25family WordDigestCondition : Type 0
26constructor WordDigestBelow
27constructor WordDigestNotZero
28constructor WordDigestZero
29constructor WordDigestNegativeThe compiler supplied declaration spans and resolved links from this source snapshot. This page does not assert that this file belongs to a checked closure.