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Accelerator.SM121.Lowering

packages/hardware/architectures/nvidia-sm121/src/Accelerator/SM121/Lowering.alpha

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family · lines 155–157

SM121SharedAddressing

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How a program's plain LDS and STS address shared memory. Accelerator.SM86's encoder writes them as [Ra.X4+off] (nvdisasm reads width byte 0x48 so on sm_86 and sm_121 alike): the address register counts 32-bit words. A program whose addresses are bytes -- the typed block models' convention -- is lowered with the scale bit cleared. LDSM has its own address form and is never rescaled.
155family SM121SharedAddressing : Type 0
156constructor SM121SharedAddressScaled
157constructor SM121SharedAddressBytes

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