Accelerator.SM121.Lowering

--------------------------------------------------------------------------- The latency rows the scheduler reads (and nothing else). The machine evaluates a function's arguments before the call, so a table call sitting in a per-cell select arm runs for every cell whether the arm is taken or not (measured: ~450 dispatch steps per cell, ~2/3 of the schedule). Each row below holds one reader's nine writer latencies and is computed once per build from the table above (the proofs still read the table itself); a scheduling step dispatches its reader's row once, and a cell extracts only its writer's entry, and only on a register match. A latency class as its row and column number.

654def sm121LowerClassTag =
655  (lambda unrestricted class : (family SM121LowerClass) .
656    (eliminate
657      SM121LowerClass
658      (lambda unrestricted current : (family SM121LowerClass) . Nat)
659      class
660      (branch SM121LowerAlu . zero)
661      (branch SM121LowerDualAlu . 1)
662      (branch SM121LowerFma . 2)
663      (branch SM121LowerWide . 3)
664      (branch SM121LowerHalfToFloat . 4)
665      (branch SM121LowerTensor . 5)
666      (branch SM121LowerVariable . 6)
667      (branch SM121LowerMemory . 7)
668      (branch SM121LowerNoResult . 8)))