Source/Packages

Accelerator.SM86.InstructionEncoding

packages/hardware/architectures/nvidia-sm86/src/Accelerator/SM86/InstructionEncoding.alpha

2,401 lines164 declarations94.5 KiBSHA-256 92e7bf9c2555

def · lines 1569–1599

sm86EncodeStoreGlobal64

Full file
STG.E.64: the register pair [value, value+1] to [address + offset]. The descriptor word differs from the 32-bit store only in the size code (byte 25 -> 27; the 128-bit store is 29), the same three codes the wide-memory descriptors carry. An mma.m16n8k16 fp32 accumulator fragment hands each thread PAIRS of adjacent columns, so a row-major epilogue needs exactly this width: a 128-bit store there overlaps the neighbouring thread and lands on an 8-byte-aligned address, which the SM faults instead of executing.

The compiler supplied declaration spans and resolved links from this source snapshot. This page does not assert that this file belongs to a checked closure.