Source/Packages

Accelerator.SM86.InstructionEncoding

packages/hardware/architectures/nvidia-sm86/src/Accelerator/SM86/InstructionEncoding.alpha

2,401 lines164 declarations94.5 KiBSHA-256 92e7bf9c2555

def · lines 1705–1717

sm86EncodeBranch

Full file
BRA (relative branch, opcode 0x947): the loop back-edge. Field layout mirrors the golden reference (offset@32(32) = relative BYTE offset from PC+16, descriptor@64(32) = 0x03800000 for a forward branch, 0x0383ffff for a backward branch). The guard predicate (@12) and negate bit (@15) and the control word (@105) are laid down by the shared instruction header, so `@!P0 BRA` reuses the SAME predicate machinery as every predicated instruction. This is a real field-packing encoder (a COMPONENT), never a golden-byte substitute; nvdisasm-verified on the SM86 profile.
1705def sm86EncodeBranch =
1706  (lambda unrestricted guard : (family SM86InstructionGuard) .
1707    (lambda unrestricted offset : (family SM86Unsigned32) .
1708      (lambda unrestricted descriptor : (family SM86Unsigned32) .
1709        (lambda unrestricted control : (family SM86Control) .
1710          (sm86EncodeInstructionFields
1711            sm86OpcodeBranch
1712            guard
1713            control
1714            (sm86InstructionPrependWord32Field
1715              sm86InstructionNaturalThirtyTwo
1716              offset
1717              (sm86InstructionOneWord32Field sm86InstructionNaturalSixtyFour descriptor)))))))

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