Source/Packages

Accelerator.SM86.InstructionEncoding

packages/hardware/architectures/nvidia-sm86/src/Accelerator/SM86/InstructionEncoding.alpha

2,580 lines175 declarations106.3 KiBSHA-256 13b25e5394ea

def · lines 1859–1871

sm86EncodeBranch

Full file
BRA (relative branch, opcode 0x947): the loop back-edge. Field layout mirrors the golden reference (offset@32(32) = relative BYTE offset from PC+16, descriptor@64(32) = 0x03800000 for a forward branch, 0x0383ffff for a backward branch). The guard predicate (@12) and negate bit (@15) and the control word (@105) are laid down by the shared instruction header, so `@!P0 BRA` reuses the SAME predicate machinery as every predicated instruction. This is a real field-packing encoder (a COMPONENT), never a golden-byte substitute; nvdisasm-verified on the SM86 profile.
1859def sm86EncodeBranch =
1860  (lambda unrestricted guard : (family SM86InstructionGuard) .
1861    (lambda unrestricted offset : (family SM86Unsigned32) .
1862      (lambda unrestricted descriptor : (family SM86Unsigned32) .
1863        (lambda unrestricted control : (family SM86Control) .
1864          (sm86EncodeInstructionFields
1865            sm86OpcodeBranch
1866            guard
1867            control
1868            (sm86InstructionPrependWord32Field
1869              sm86InstructionNaturalThirtyTwo
1870              offset
1871              (sm86InstructionOneWord32Field sm86InstructionNaturalSixtyFour descriptor)))))))

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