Source/Packages

Accelerator.SM86.InstructionEncoding

packages/hardware/architectures/nvidia-sm86/src/Accelerator/SM86/InstructionEncoding.alpha

2,580 lines175 declarations106.3 KiBSHA-256 13b25e5394ea

def · lines 970–972

sm86Float8FormatNatural

Full file
F2FP.SATFINITE.{E4M3,E5M2}.F32.PACK_AB_MERGE_C: the merge register at bit 64, its half at bit 72 (1: H1), bit 76 the format (1: E4M3, 0: E5M2), bits 77, 78, 87 and 90 set (ptxas 12.9 for sm_90a through Triton, Inductor's quantization kernels: 0x...723e / 0x04807108 for E4M3 with merge R8.H1, 0x0480610a for E5M2 with R10.H1)
970def sm86Float8FormatNatural = (lambda unrestricted format : (family SM86Float8Format) .
971  (eliminate SM86Float8Format (lambda unrestricted current : (family SM86Float8Format) . Nat) format
972    (branch SM86Float8E4M3 . 1) (branch SM86Float8E5M2 . 0)))

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