Source/Packages

Accelerator.SM86.InstructionEncoding

packages/hardware/architectures/nvidia-sm86/src/Accelerator/SM86/InstructionEncoding.alpha

2,580 lines175 declarations106.3 KiBSHA-256 13b25e5394ea

def · lines 979–982

sm86FloatOperationOpcode

Full file
FADD / FMUL / FFMA with modifiers (ptxas 12.9 for sm_90a, register forms; Proof.FloatArithmeticContract holds both encoders to its words): the opcode 0x221 / 0x220 / 0x223 (FMUL with bit 86 set, as plain FMUL), the addend at bit 64 (FFMA), |right| bit 62, -right bit 63, -left bit 72, |left| bit 73, -addend bit 75, .SAT bit 77, the rounding bits 78..79 (RN 0, RM 1, RP 2, RZ 3), .FTZ bit 80
979def sm86FloatOperationOpcode = (lambda unrestricted operation : (family SM86FloatOperation) .
980  (eliminate SM86FloatOperation (lambda unrestricted current : (family SM86FloatOperation) . Nat) operation
981    (branch SM86FloatOperationAdd . sm86OpcodeFloatAdd) (branch SM86FloatOperationMultiply . sm86OpcodeFloatMultiply)
982    (branch SM86FloatOperationFusedMultiplyAdd . sm86OpcodeFloatFusedMultiplyAdd)))

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