ASSUMED, and stated as an assumption: the cycles after issue before a
fixed-latency form's destination (register or predicate) may be read --
6 for every such form, above the 4 published for Ampere's FP32 and
integer pipes. Variable-latency forms (loads, S2R, SHFL, MUFU, HMMA)
deliver through a scoreboard barrier instead, and forms with no
destination deliver nothing (0). A program accepted under this table
that a card computes wrongly refutes it: silicon runs of stall-compacted
programs are its evidence.
414def sm86FixedLatencyCycles : Nat = 6The compiler supplied declaration spans and resolved links from this source snapshot. This page does not assert that this file belongs to a checked closure.