HMMA.16816.F32: a fixed-latency result, as ptxas schedules it for sm_86
(no scoreboard; a dependent HMMA 24 cycles after its producer, a store
of the result 23 -- nvdisasm -hex of a dependent mma.sync chain on the
DGX Spark, 2026-09-26; sm_121's is 29, Accelerator.SM121.Lowering's
tensor class). Its sources are read at issue. An HMMA that declares a
write barrier is ordered by it instead (the older products do).
463def sm86TensorLatencyCycles : Nat = 24The compiler supplied declaration spans and resolved links from this source snapshot. This page does not assert that this file belongs to a checked closure.