Source/Packages

Accelerator.SM86.Operands

packages/hardware/architectures/nvidia-sm86/src/Accelerator/SM86/Operands.alpha

699 lines54 declarations58.4 KiBSHA-256 ac21d61cced1

def · lines 68–68

sm86RegisterLimit

Full file
The most registers a thread's allocation holds: 256 (the QMD's count in granules; CUDA's own kernels on the RTX 3070 name up to R253 and are allocated 256, e.g. cuBLAS's 254-register s1688 products). A register index is a byte, so a generator that numbers registers past it does not fail -- its indices wrap onto registers already in use; a generator states its span and is admitted against this.
68def sm86RegisterLimit : Nat = 256

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