Source/Packages

Realization.Nvidia.SM86.IndexedRowScatterOrderedSM86

packages/realizations/cooperative/nvidia-sm86/src/Realization/Nvidia/SM86/IndexedRowScatterOrderedSM86.alpha

162 lines31 declarations8.5 KiBSHA-256 2c5e7fb343d9

def · lines 160–162

indexedRowScatterOrderedSM86Program

Full file
The scan reuses address registers across global loads. An LDG write barrier retires its result but does not guarantee that its address read has finished; serialize those late reads before reusing an address. This only changes controls, so the loop's relative branch lengths stay valid. See the read-barrier ownership check in SM86.Scoreboard.
160def indexedRowScatterOrderedSM86Program =
161  (lambda unrestricted width : Nat . (lambda unrestricted rows : Nat .
162    (sm86GuardLateReads (indexedRowScatterOrderedSM86ProgramRaw width rows))))

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