Source/Packages

Realization.Nvidia.SM86.LinearStepPlanSM86

packages/realizations/cooperative/nvidia-sm86/src/Realization/Nvidia/SM86/LinearStepPlanSM86.alpha

348 lines59 declarations18.5 KiBSHA-256 ff3ec4d2f314

def · lines 25–25

linearStepPlanArenaBase

Full file
The device side of the checked linear step, declared the way Bob and Coppelius declare theirs: a device arena with a placement certificate, one typed code region, one launch whose parameter block names the four data regions and the learning rate, and one submission. The NVIDIA backend (compiler-native-encode of the plan, at build time) derives the program table, the QMD, the pushbuffer and the GPFIFO from this; nothing here joins bytes or knows a wire layout. The arena. Every address below is arena base + resident offset, and the residents' placement is decided by Runtime.ArenaCertificate in Proof.CheckedLinearStep: aligned, inside the arena, pairwise disjoint.
25def linearStepPlanArenaBase : Nat = 0x0000_0008_0000_0000

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