Realization.Nvidia.SM86.StreamingAttentionSM86

=========================================================================== The key pass with each query sub-tile staged in shared memory, as the forward and query passes. A step's operands are Q's and dO's 32 rows (plain for S^T and dP^T, read transposed by LDSM.T for dK and dV, the same values in the same lanes as the register kernel's Q^T and dO^T loads) and the sub-tile's 32 L and D words (global loads, each pair its own pointer). The 64 threads copy row r + 8 i, chunk c of each plane (thread 8 r + c). The prologue's K and V fragment loads keep their own address pairs, so no load address is ever re-formed before its late read and the late-read guard is not needed.

2706def sksQueryTile : Nat = 4608